Cause : Topology: Too many components on one line. For the selected communications clock cycle, too many DRIVE-CLiQ components are connected to one line of the Control Unit.

Fault value (r0949, interpret hexadecimal):

xyy hex: x = fault cause, yy = component number or connection number.

1yy:

The communications clock cycle of the DRIVE-CLiQ connection on the CU is not sufficient for all read transfers.

2yy:
The communications clock cycle of the DRIVE-CLiQ connection on the CU is not sufficient for all write

transfers.
3yy:
Cyclic communication is fully utilized.

4yy:
The DRIVE-CLiQ cycle starts before the earliest end of the application. An additional dead time must be added to
the control. Sign-of-life errors can be expected.

5yy:
Internal buffer overflow for net data of a DRIVE-CLiQ connection.

6yy:
Internal buffer overflow for receive data of a DRIVE-CLiQ connection.

7yy:
Internal buffer overflow for send data of a DRIVE-CLiQ connection.

8yy:
The component clock cycles cannot be combined with one another

900:
The lowest common multiple of the clock cycles in the system is too high to be determined.

901: The lowest common multiple of the clock cycles in the system cannot be generated with the hardware.

Remedy:

Check the DRIVE-CLiQ connection.

Reduce the number of components on the DRIVE-CLiQ line involved and distribute these to other DRIVE-CLiQ sockets of the Control Unit. This means that communication is uniformly distributed over several lines. When using DCC, the scope of the DCC logic can also become a problem.

Re fault value = 1yy - 4yy in addition:
- increase the sampling times (p0112, p0115, p4099).
- reduce the DCC logic

Re fault value = 8yy in addition:
- check the clock cycles settings (p0112, p0115, p4099). Clock cycles on a DRIVE-CLiQ line must be perfect integer
multiples of one another. As clock cycle on a line, all clock cycles of all drive objects in the previously mentioned
parameters apply, which have components on the line involved.

Re fault value = 9yy in addition:
- check the clock cycles settings (p0112, p0115, p4099). The lower the numerical value difference between two clock
cycles, the higher the lowest common multiple. This behavior has a significantly stronger influence, the higher the
numerical values of the clock cycles.